Conventional system architectures for low power operations can incorporate both a dynamic random access memory (DRAM) and Flash (Flash Electrically Programmable and Eraseable Read Only Memory) memory as part of the memory hierarchy. Standby power can be reduced by powering off the DRAM. However, DRAM is a volatile memory that loses its data in the absence of power. Thus, if DRAM data is needed when the system starts up again, such data is stored in the Flash memory. Copying data from DRAM to Flash memory when entering a standby mode, and reading data back from the Flash memory into DRAM when entering active mode, adds to system power and latency.
In many conventional mobile systems, energy is saved by removing power from various subsystems when possible. However, to ensure continuity of operation, user states must first be saved in a subsystem that remains powered or in a nonvolatile memory, such as Flash memory. For example in a laptop computer, a “suspend to ram” operation saves all processor states in memory, then powers off the processor. The memory remains powered. When resuming, the processor is powered up and the state restored. In a “suspend to disk” operation, the system state is saved to disk, and then the majority of the platform can be powered down. In small mobile devices, such as smart phones and tablets, nonvolatile memory serves a function like that of the disk in a laptop computer.
The speed with which these save/restore functions can be performed, and the energy cost of the save/restore functions themselves, can affect the energy saving benefits of the system. In general, the save/restore functions must be both fast and low energy. When this is achieved, energy savings can result from performing save/restore more frequently, equivalently, more aggressively. In conventional smart phones and tablet computing devices the path used by the save/restore function goes through a system-on-chip (SoC) device, and is often performed in software. In addition, in such conventional systems, DRAM and Flash have relatively low bandwidth paths to the SoC.
Conventional memory systems are known that pair static random access memory (SRAM) cells with silicon-oxide-nitride-oxide-silicon (SONOS) type storage elements. Such memory systems can perform a bit-to-bit copy of SRAM data to SONOS elements. However, a drawback to SONOS technology can be the relatively high voltages needed to program SONOS elements. This can present process integration challenges, and require more power, as power is proportional to voltage squared. In addition, the one-to-one pairing of SRAM cells to SONOS elements results in a hardwired configuration between the SRAM storage space and the SONOS storage space. That is, such systems do not have any flexibility to configure which areas will be saved/restored and which areas will not.
FIG. 18 shows a conventional system 1800 that can be included in a smart phone or tablet computing device. A conventional system 1800 can include an SoC 1801, a DRAM section 1805, and Flash memory section 1803. DRAM and Flash memory sections (1805, 1803) can have separate data paths to the SoC 1801. In FIG. 18, a data path 1807-0 between Flash memory 1803 and SoC 1801 can be 32-bits wide, while a data path 1807-1 between DRAM 1805 and SoC 1801 can be 32- or 64-bits wide. In order to remove power from the SoC 1801, the state of the SoC 1801 and the data stored by the DRAM section 1805 must be saved. A conventional system 1800 can execute a save operation in one of two ways. Either power is maintained to the DRAM at all times or the relevant DRAM state is copied to the Flash memory before removing power from the DRAM. Such a copy operation can be quite slow due to the nature of Flash memory (erasure of one or more sectors followed by programming of data) and the need to move the data through the SoC 1801.
In a restore operation, data can be transferred, via SoC, from Flash memory 1803 to DRAM 1805. Until the restore operation is complete, other operations by system 1800 may not be possible.